This invention relates to a non-volatile semiconductor memory having an array of non-volatile memory cells and relates to a method for driving a non-volatile semiconductor memory.
Many such non-volatile semiconductor memories have been known in the art. Japanese Patent Application (Pub. No. 5-28778) and Japanese Patent Application (Pub. No. 4-15953) each disclose a non-volatile semiconductor memory, wherein source decoders are connected to separate sourcelines associated with separate memory cell sources. Referring now to FIGS. 42-44, a non-volatile semiconductor memory of a conventional type having an array of nonvolatile memory cells is illustrated. FIG. 42 outlines in block form a conventional non-volatile semiconductor memory structure. Shown in FIG. 42 are a memory cell array 101, a row decoder circuit 102, a column decoder circuit 103, and a source decoder circuit 104. FIG. 43 is a circuit diagram depicting a part of the memory cell array 101. Referring to FIG. 43, therein are shown TRANSISTORS T11-Tmn, WORDLINES W1-Wm, BITLINES B1-Bn, SOURCELINES S1-Sm, and COLUMN SELECTION TRANSISTORS ST1-STn. Each TRANSISTOR T11-Tmn has a source, a drain, and a gate underlying which is a floating gate (i.e., a capacitance section). The memory cell array 101 has an array of memory cells arranged in m rows and n columns, each memory cell having therein a TRANSISTOR T. Each of the gates of TRANSISTORS T11-T1n in the first row is coupled to WORDLINE W1, and each of the gates of TRANSISTORS T21-T2n in the second row to WORDLINE W2, and each of the gates of TRANSISTORS Tm1-Tmn in the mth row to WORDLINE Wm. Each of the sources of TRANSISTORS T11-T1n in the first row is coupled to SOURCELINE S1, and each of the sources of TRANSISTORS T21-T2n in the second row to SOURCELINE S2, and each of the sources of TRANSISTORS Tm1-Tmn in the mth row to SOURCELINE Sm. Each of the drains of TRANSISTORS T11-Tm1 in the first column is coupled to BITLINE B1, and each of the drains of TRANSISTORS T12-Tm2 in the second column to BITLINE B2, and each of the drains of TRANSISTORS T1n-Tmn in the nth column to BITLINE Bn. Such arrangement is called an NOR-type structure in which transistors are arranged at points where WORDLINES W1-Wm and BITLINES B1-Bn cross one another. Here, WORDLINES W1-Wm run parallel with SOURCELINES S1-Sm. Whereas WORDLINES W1-Wm are connected to corresponding ROW DECODERS RD1-RDm of the row decoder circuit 102, SOURCELINES S1-Sm are connected to corresponding SOURCE DECODERS SD1-SDm of the source decoder circuit 104. BITLINES B1-Bn run in the cross direction to WORDLINES W1-Wm and SOURCELINES S1-Sm and are connected to the column decoder circuit 103 via SENSE AMPLIFIERS SA1-SAn. If, in a TRANSISTOR T, the capacitance section has a memory state of "one" when the electric potential of the gate is above Vt (the threshold voltage) and when V.sub.DS (the drain-source voltage) is above a predetermined value, then a current flows through a PATH P (P11-Pmn) extending from a certain location of a BITLINE B to a SOURCELINE S through TRANSISTOR T. On the other hands, if the capacitance section has a memory state of "zero", then no electric current flows.
Referring now to FIG. 44, a reading operation of extracting data out of a conventional non-volatile semiconductor memory is explained. The writing and erasing of a non-volatile semiconductor memory, e.g., an EEPROM (electrically-erasable, electrically-programmable, read-only-memory), is performed by greatly changing a transistor threshold voltage level. If a transistor is in a high threshold voltage state above Vcc (the reading supply voltage), this is called a "zero" state. On the other hand, if a transistor is in a low threshold voltage state below Vcc, this is called a "one" state. These transistor state definitions are used hereinafter throughout the specification.
A conventional reading operation of extracting data out of, for example, a memory cell having therein TRANSISTOR T22 (hereinafter called MEMORY CELL (T22)) is now explained. WORDLINE W2, which is a selected wordline, is set to Vcc (the reading supply voltage), for example, 5 V. On the other hand, WORDLINES W1, W3-Wm, which are deselected wordlines, are set to Vss (the ground level), for example, 0 V. At the same time, SOURCELINE S2, which is a selected sourceline, is set to Vss. On the other hand, SOURCELINES S1, S3-Sm), which are deselected sourcelines, are set to Vrm (the reading intermediate voltage level), for example, 1 V, or are brought to a "float" while being kept at Vrm. BITLINE B2, which is a selected bitline, is set to Vrm via a corresponding sense amplifier. On the other hand, BITLINES B1, B3-Bn, which are deselected bitlines, are set to Vss or are brought to a "float" while being kept at Vss. Practically, a bitline is connected to a respective sense amplifier and a slight bitline potential variation from Vrm occurs. However, for the purpose of simplifying the description, it is assumed that the bitline potential stays constant. Although it has been described that deselected sourcelines and deselected bitlines may be brought to a "float", the description will be made on condition that a deselected sourceline is set to Vrm and a deselected bitline is set to Vss. MEMORY CELL (T22) in the "zero" state passes no current and no current flows through BITLINE B2 accordingly. If MEMORY CELL (T22) has a "one" state, a current flows from BITLINE B2 to SOURCELINE S2 through MEMORY CELL (T22). By detecting the presence or absence of a current flowing in BITLINE B2, a read is accomplished.
In the above-described semiconductor memory, SOURCELINE S1 is at Vrm so that SOURCELINE S1 and BITLINE B2 are at the same electric potential. This produces greater resistance to a current flowing from BITLINE B2 to SOURCELINE S1. Therefore, MEMORY CELL (T12) is unlikely to be misread, thereby increasing the margin of reading.
In semiconductor memories having an array of non-volatile memory cells, control of writing and erasing operations may not be a solution to improving variations in the memory cell threshold-voltage and a memory cell is likely to be over-depleted to have a negative threshold voltage. During fabrication of non-volatile semiconductor memories, variations in the memory cell threshold voltage are caused by processing variations including variations in the impurity concentration and variations in the size. Additionally, as the level of integration increases, dimensional errors and the like produce larger threshold voltage variations. Further, the semiconductor memory industry is now trying to reduce the operating voltage of non-volatile semiconductor memories of large integration as low as possible, to provide low power memories for the purpose of solving heat problems. Therefore, the center of the distribution of threshold voltages among individual memory cells now shifts to lower voltage ranges. Such, however, produces some problems. For example, as the dimensions of non-volatile semiconductor memories decrease and as the scale of integration increases, the probability of part of memory cells in an array being over-depleted increases.
If MEMORY CELL (T22) in the "one" state is read when MEMORY CELL (T12), which is a deselected memory cell and which is coupled to the selected BITLINE B2, is in an over-depletion state, then an electric current flows through BITLINE B2 and the potential of BITLINE B2 drops. At this point in time, a current flows from SOURCELINE S1 at Vrm into BITLINE B2 through MEMORY CELL (T12), whereupon the potential of BITLINE B2 is brought back to Vrm. If BITLINE B2 makes no potential transitions, this may cause SENSE AMPLIFIER SA2 coupled to BITLINE B2 to make an incorrect detection that MEMORY CELL (T22) has a "zero" state, although MEMORY CELL (T22) has in fact a "one" state. Read errors may result. Conventional non-volatile semiconductor memories produce the problem that read errors are likely to occur because of existence of depleted memory cells.
In a conventional non-volatile semiconductor memory, in a reading operation (see FIG. 44), even when a deselected memory cell, e.g., MEMORY CELL (T11), is slightly depleted, an electric current flows from SOURCELINE S1 into BITLINE B1 which is a deselected bitline. Such a current causes no read errors because it flows in a deselected bitline but increases the amount of power required. In a conventional non-volatile semiconductor memory, a deselected sourceline and a deselected bitline are brought to a "float". However, in such a case, a transitional current is created for every reading operation, and low power dissipation cannot be accomplished during a fast reading operation.
Even if writing and erasing operations are controlled by performing a verification operation, there still exist large variations in the memory cell property and a memory cell is depleted having a threshold voltage of 0 V or less. Variations in the memory cell threshold voltage are caused by processing variations including variations in the impurity concentration and variations in the size. Additionally, as the level of integration increases, dimensional errors and the like produce larger threshold voltage variations.
The threshold voltage of non-volatile memory transistors, especially the threshold voltage of non-volatile memory transistors having a stack-type floating gate, is drain voltage-dependent. This is explained with reference to FIGS. 46, 47a-b and using formulas expressing the relationship of capacitance versus electric potential. FIG. 46 shows in cross section a transistor having a stack-type floating gate structure. FIGS. 47a, 47b are graphs each showing the relationships of drain current, Id, versus gate voltage, Vg in trial products of the present invention having a stack-type floating gate structure and in usual MOS transistors. In FIG. 46, 61 is a floating gate. 62 is a control gate. 63 is a drain. 64 is a source. 1 is a semiconductor substrate. Dielectric layers are not shown in the figure. Cc is the floating gate-control gate capacitance. Cd is the floating gate-drain capacitance. Cs is the floating gate-source capacitance. Cb is the floating gate-semiconductor substrate capacitance. Vcg is the voltage applied to the control gate 62. Vfg is the electric potential of the floating gate 61. Vd is the drain voltage. Vs is the source voltage. Vb is the electric potential of the semiconductor substrate 1. As shown in FIG. 47b, in the usual MOS transistor there is almost no difference in the threshold voltage between when Vd=0.1 V and when Vd=2.0 V. A threshold voltage viewed from a floating gate, VTfg, is almost independent of Vd and stays constant. On the other hand, as shown in FIG. 46, the floating gate 61 and the drain 63 are in capacitive coupling relationship. Upon application of Vd to the drain 63, the potential of the Floating gate 61, Vfg, drops by rd Vd (rd=Cd/Ct) as shown in the following formulas. Additionally, a threshold voltage viewed from the control gate 62, VTcg, drops by rd Vd/r because of Vd. As a result, as shown in FIG. 47a, in the non-volatile memory transistor having a stack-type floating gate structure, there is a difference of about 0.3 V (usually 0.2-0.4 V) in the threshold voltage between when Vd=0.1 V and when Vd=2.0 V.
Ct=Cc+Cd+Cs+Cb PA1 r=Cc/Ct, rd=Cd/Ct, rs=Cs/Ct, rb=Cb/Ct PA1 Vcg=(Vfg-rd Vd-rs Vs-rb Vb)/r PA1 VTcg0=(VTfg -rs Vs -rb Vb )/r PA1 VTcg=VTcg0-rd Vd/r PA1 an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain; PA1 a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array; PA1 a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array; PA1 a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array; PA1 a row decoder circuit for selecting among said plurality of wordlines; PA1 a column decoder circuit for selecting among said plurality of bitlines; PA1 a source decoder circuit for selecting among said plurality of sourcelines; PA1 a plurality of anisotropic resistance sections; PA1 wherein: PA1 a plurality of sense amplifiers, each of the sense amplifiers requiring a reference electric potential; PA1 a plurality of reference dummy cells, each of the reference dummy cells being arranged in each said bitline; PA1 wherein: PA1 said memory comprising: PA1 a plurality of sense amplifiers, each of said sense amplifiers requiring a reference electric potential; PA1 a plurality of reference dummy cells, each of said reference dummy cell being arranged in a said bitline; PA1 wherein: PA1 an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain; PA1 a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array; PA1 a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array; PA1 a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array; PA1 a row decoder circuit for selecting among said plurality of wordlines; PA1 a column decoder circuit for selecting among said plurality of bitlines; PA1 a source decoder circuit for selecting among said plurality of sourcelines; PA1 a plurality of anisotropic resistance sections; PA1 wherein: PA1 said non-volatile semiconductor memory comprising: PA1 an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain; PA1 a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array; PA1 a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array; PA1 a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array; PA1 a row decoder circuit for selecting among said plurality of wordlines; PA1 a column decoder circuit for selecting among said plurality of bitlines; PA1 a source decoder circuit for selecting among said plurality of sourcelines; PA1 said drive method comprising the steps of:
.thrfore.Vfg=r Vcg+rd Vd+rs Vs+rb Vb PA2 each said anisotropic resistance section is arranged in a path from a said bitline to a said sourceline through a said transistor; PA2 each said anisotropic resistance section has voltage-current properties which are different for different levels of voltages applied across said anisotropic resistance section; PA2 each said anisotropic resistance section has a forward direction in which a current flows therethrough with lesser resistance and a reverse direction in which a current flows therethrough with greater resistance. PA2 the reference electric potential is generated in one of two adjoining bitlines. PA2 an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain; PA2 a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array; PA2 a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array; PA2 a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array; PA2 a row decoder circuit for selecting among said plurality of wordlines; PA2 a column decoder circuit for selecting among said plurality of bitlines; PA2 a source decoder circuit for selecting among said plurality of sourcelines; PA2 a plurality of anisotropic resistance sections; PA2 wherein: PA2 selecting, from among said plurality of bitlines, a bitline associated with a memory cell to be read by means of said column decoder circuit; PA2 selecting, from among said plurality of sourcelines, a sourceline associated with said memory cell by means of said source decoder circuit; PA2 setting the electric potential of said selected bitline and the electric potential of said selected sourceline such that the electric potential relationship of said selected bitline versus said selected sourceline agrees with said forwarding direction of said anisotropic resistance section, and setting the higher of said selected bitline's electric potential and said selected sourceline's electric potential as a reading electric potential; PA2 setting the electric potential of deselected sourcelines to an electric potential level above the lower of said selected bitline's electric potential and said selected sourceline's electric potential but below said reading electric potential. PA2 said reference electric potential is generated in one of two adjoining bitlines; PA2 said drive method further comprising the steps of: PA2 each said anisotropic resistance section is arranged in a path from a said bitline to a said sourceline through a said transistor; PA2 each said anisotropic resistance section has voltage-current properties which are different for different levels of voltages applied across said anisotropic resistance section; PA2 each said anisotropic resistance section has a forward direction in which a current flows therethrough with lesser resistance and a reverse direction in which a current flows therethrough with greater resistance PA2 wherein: PA2 selecting, from among said plurality of sourcelines, a source line associated with a memory cell of said memory cells to be read by means of said source decoder circuit; PA2 selecting, from among said plurality of wordlines, a wordline associated with said memory cell; PA2 setting the electric potential of said selected wordline to a given electric potential level; PA2 setting the electric potential of all of said bitlines to a first electric potential level; PA2 setting the electric potential of said selected sourceline to a second electric potential level higher than said first electric potential level for reading said memory cell.
There are produced variations in the memory cell threshold voltage because of the heterogeneous distribution of impurity concentrations during manufacture and because of the condition of how voltages are applied to individual sections. On the whole, the distribution of threshold voltages among individual memory cells falls within a certain range. FIG. 45 is a graph showing an example of the distribution of threshold voltages. In the graph, the abscissa indicates the non-volatile memory threshold voltage and the ordinate indicates the frequency. In an NOR-type memory cell array, a threshold voltage is controlled by a verification operation to have a rather high value, to eliminate read errors. Curve A-B of FIG. 45 illustrates a type of memory cell threshold voltage Vt distribution in the high threshold voltage condition (i.e., the "zero" state). Curve C-D of FIG. 45 illustrates a type of memory cell threshold voltage Vt distribution in the low threshold voltage condition (i.e., the "one" state). As already explained, in a reading operation, Vt, which is Vd-dependent, drops 0.2-0.4 V, resulting in the threshold voltage Vt distribution represented by Curve A'-B' and resulting in the threshold voltage Vt distribution represented by Curve C'-D'.
In the low threshold voltage condition, in order to guarantee a reading current (above 50 .mu.A) that starts flowing when Vccmin (the minimum of Vcc) is applied to the control gate of a memory cell, the memory cell must have a threshold voltage lower by about 1.0 V than Vccmin (see Point B' of FIG. 45), although such depends on the sensitivity of sense amplifier as well as on the memory cell mutual conductance. In an NOR-type memory cell array, in order to prevent a deselected memory cell from being misread, a sum of leakage currents of deselected memory cells coupled to a single bitline must be sufficiently lower than a reading current (above 50 .mu.A), and a memory cell in the low threshold voltage condition must have a threshold voltage above 0.5 V (see Point A'of FIG. 45).
If Vcc=3 V and Vccmin=2.7 V in the low threshold voltage condition, then a potential difference between Point A' and Point B of FIG. 45 must be below 1.2 V. If it is assumed that there is a threshold voltage drop of 0.2-0.4 V caused by Vd, then the width of the Curve A-B threshold voltage distribution must be below 1.0 V. These are the minimum requirements. In an actual memory, control margins for verification must be considered. Much more severe control on the distribution of threshold voltages Vt among individual memory cells is required, particularly in the low threshold voltage condition. The semiconductor industry is now trying to reduce the operating voltage of non-volatile semiconductor memories of large integration, to accomplish low power dissipation for solving heat problems. As Vcc (the reading voltage) becomes lower, it is necessary to control the threshold voltage distribution in a much more severe manner. For example, where Vcc is around 3.0 V, even a drop in the threshold voltage caused by Vd cannot be ignored. This results in increasing the probability of some memory cells being over-depleted.
A memory cell in the high threshold voltage condition must have an off state even when Vccmax (the maximum of Vcc) is applied thereto. A leakage current of that memory cell must be sufficiently lower than a reading current (above 50 .mu.A) but greater than Vccmax by about 0.5 V (see Point C' of FIG. 45). Apart from the above, there are no other rigorous limitations for a memory cell in the high threshold voltage condition. Greater threshold voltage provides better advantage when considering reading operations only, thereby providing a greater threshold voltage control margin.
When considering improvement in the writing operations and improvement in the number of times a write/erase operation is executed, a lower threshold voltage is preferable. However, when considering only reading operations, there is no need to lower a threshold voltage. The present invention pertains to reading operations, so it is assumed here that greater memory cell threshold voltage provides better advantage.
In a reading operation of extracting data out of the FIG. 42 non-volatile semiconductor memory, Vrm (the reading intermediate voltage) is applied to a selected bitline coupled to the drain of a target memory cell. This causes the threshold voltage of deselected memory cells coupled to that selected bitline to drop, thereby increasing the possibility that over-depletion occurs. Vrm is applied to the drains of MEMORY CELLS (T12) and (Tm2) as well as the sources thereof and their threshold voltages viewed from the floating gates increase by the substrate bias effect. However, if Vrm=1.0 V, then the substrate bias effect is only about 0.1 V and is cancelled by a drop in the threshold voltage caused by Vs. Accordingly the threshold voltage viewed from the control gate decreases more.
Accordingly, if MEMORY CELL (T22) in the low threshold voltage condition is read when MEMORY CELL (T12), which is a deselected memory cell and which is coupled to the selected BITLINE B2, is being over-depleted, then an electric current flows through BITLINE B2, and BITLINE B2 slightly drops in potential. At this point in time, a current flows from SOURCELINE S1 at Vrm into BITLINE B2 through MEMORY CELL (T12), whereupon the potential of BITLINE B2 is brought back to Vrm. If BITLINE B2 makes no electric potential transitions, this may cause SENSE AMPLIFIER SA2 coupled to BITLINE B2 to make an incorrect detection that MEMORY CELL (T22) has a high threshold voltage condition, although MEMORY CELL (T22) has in fact has a low threshold voltage condition. Reading errors may result. Additionally, improvements in the mutual conductance necessary for accomplishing high-speed reading operations become difficult to accomplish.